1. Field of the Invention
The present invention is directed to methods and systems for limiting supply bounce, such as power supply and/or ground bounce.
2. Background Art
There is a trend towards increasing the number of digital I/O pads on integrated circuits (“ICs”) to increase the integrated functionality and the number of bits of data processed. When multiple digital I/O pads switch simultaneously, currents in supply (power supply and/or ground) lines associated with the digital I/O pads tend to vary with time. Such transient current changes interact with supply line inductances to cause excursions in supply voltages. Thus supply (power supply and/or ground) voltages may oscillate above and/or below normal levels. This is called supply bounce or VDD/GND bounce. The increase of positive power supplies above normal operating levels and the decrease of ground below normal operating levels leads to relatively large amounts of current flow between the power supplies and pads. This limits the number of output pads which can simultaneously switch at any given time.
Methods and systems are therefore needed to limit supply bounce.